Field of the Invention
The present invention relates to a circuit configuration for driving a programmable link and to the use thereof in a memory chip.
In memory chips, for example synchronous dynamic random access memories (SDRAMs), having a memory space of 256 megabits, for example, memory cells which can compensate for production-dictated failures of individual memory cells are usually provided for the purpose of providing redundancy. For this purpose programmable links, also referred to as fuses, are provided, which enable defective memory cells to be replaced by intact replacement cells. A few thousand fuses are provided in 256-megabit RAMs by way of example.
The fuses can be permanently reprogrammed with regard to their state of conduction in a known manner either by an energy pulse in the form of a laser or by an electrical pulse, for example a voltage or current pulse. In this case, a distinction is made between what are called fuses, which can be put into a non-conducting (high-impedance) state from a conducting (low-impedance) state by an energy pulse described, and antifuses, which can be changed from a non-conducting state to a conducting state by application of an energy pulse.
In semiconductor memory chips, the so-called programming, activation or blowing of fuses, which is a one-time operation which permanently changes the fuse from a low-impedance to a high-impedance state or from a high impedance state to a low-impedance state, has usually been effected hitherto by a laser prior to encapsulation of the memory chip. However, this is associated with the disadvantage that it is no longer possible to repair defective memory cells after encapsulation of the chip.
Furthermore, it is customary to replace the memory cells of an entire word line in a memory chip, but the replacement of individual addresses of memory cells, so-called single address repair, is desirable.
When fuses are blown by current or voltage pulses, which is also possible, in principle, after encapsulation of a chip, the problem can arise that the simultaneous blowing of a plurality of fuses entails an impermissibly high current consumption in the circuit.
In a mass memory chip, it is normally desirable, on the one hand, to program a replacement of defective memory cells by redundant, intact memory cells in real time, since, in the case of present-day memory chip clock rates of above 100 MHz, it is not possible to blow fuses within a clock period, that is to say before the next potential access to the repaired memory cell. On the other hand, such fast memories are usually volatile memories, and so permanent programming of a fuse is additionally necessary.
It is accordingly an object of the invention to provide a circuit configuration for driving a programmable link that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which it is possible to rapidly read from and write to volatile memories coupled to the drive circuit for the programmable link.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for driving a programmable link. The circuit configuration contains a volatile memory having an address input and a volatile memory cell connected to the address input for feeding in an information item. The volatile memory is coupled to the programmable link for permanently storing a datum from the volatile memory cell to the programmable link. A shift register has a register cell coupled to the volatile memory cell in a read direction and in a write direction for a data transfer between the register cell and the volatile memory cell.
The programmable link may be configured as a fuse or as an antifuse.
A programmable link configured as a fuse undergoes transition from a low-impedance to a high-impedance state of conduction upon application of an energy pulse. A programmable link configured as an antifuse undergoes transition from a high-impedance to a low-impedance state of conduction upon application of an energy pulse. The transition from one state of conduction to another is normally an irreversible operation in both cases.
For the addressing of a defective memory cell of an SDRAM or another memory module it is possible to provide a plurality of bits, for example, for each of which a circuit configuration described is provided. In this case, the respective shift registers may be connected to one another serially in order to form a shift register chain. In other words, an input of one shift register may be connected to an output of another shift register. With the shift register which is coupled to the register cell of the shift register in a read direction and in a write direction, it is possible to serially read from and write to the memory cells of the respective volatile memories respectively assigned to a programmable link. This requires a particularly low outlay on circuitry. The writing and reading can be effected particularly rapidly with the circuit configuration described.
With the programmable link, the information stored temporarily in the volatile memory cell is stored permanently. With the shift register described, the information items that are to be stored permanently, for example, are written to the respective memory cells of the assigned programmable links. Furthermore, the circuit configuration described enables a rapid read-out of the information items stored in the programmable links via the volatile memory, which is coupled to the programmable link for the read-out thereof, and also by use of the shift register or a shift register chain formed from a plurality of shift registers.
By way of example, a bit of an address of a defective memory cell, to be repaired, of an SDRAM can be stored in the memory cell of the volatile memory.
The coupling between the volatile memory and the programmable link for the permanent storage of a datum from the memory cell of the volatile memory can be effected by a drive circuit, for example, which provides an energy pulse necessary for blowing or programming the programmable link (fuse). In this case, the read direction is understood to be the data transfer from the memory cell or an output of the memory cell of the volatile memory into the shift register. In this case, the write direction is understood to be the data transfer from the register cell of the shift register to the memory cell or an input of the memory cell of the volatile memory.
In one preferred embodiment of the present invention, a write transistor is provided, which is connected to a write input by its control input and which couples the register cell to the memory cell by its controlled path and a read transistor is provided, which is connected to a read input by its control input and which couples an output of the memory cell to the shift register by its controlled path.
In a further preferred embodiment of the invention, a drive circuit is provided for driving the programmable link with an energy pulse, the drive circuit being coupled to the memory cell of the volatile memory for the communication of a data signal. The drive circuit enables a datum to be read out in a simple manner from the volatile memory and this data signal to be fed to the drive circuit. The fuse either may or may not be blown or programmed by the energy pulse, depending on whether, for example, a zero or a one is read out.
In a further preferred embodiment of the invention, the drive circuit for controlling the energy pulse is coupled to the shift register for the communication of an activation signal. In addition to the possibility of writing to and reading from the memory cell in the volatile memory by the shift register, the shift register can simultaneously be used for activating a fuse blowing operation. This enables targeted subsequent blowing of fuses which, for example, could not be programmed during a first programming attempt. Moreover, an impermissibly high blowing current as a result of blowing too many programmable links can simultaneously be prevented by virtue of the targeted selection of individual or a plurality of programmable links for blowing by the shift register. Moreover, the dual function described for the shift register enables a particularly space-saving circuit construction.
In a further preferred embodiment of the invention, the drive circuit has an AND logic circuit, which ANDs a data input with an activation input and has an output coupled to the programmable link. In the case of the AND logic circuit described in the drive circuit, the programmable link is blown given the presence of a blowing voltage only when an activation signal is present at an activation input and a data signal is present at a data input, which signal may be provided for example in the memory cell of the volatile memory.
In a further preferred embodiment of the present invention, the drive circuit has a blowing transistor, which, on the input side, is coupled to the volatile memory and which, at an output connected to the programmable link, provides an energy pulse. Accordingly, three conditions may be necessary for the provision of the energy pulse. The data signal must have a logic one, the activation signal must have a logic one, and a blowing voltage must be present at the blowing transistor. If all three conditions are met, the programmable link, which may be configured as an antifuse, for example, can be blown.
In a further preferred embodiment of the invention, the shift register has a respective switch on the input side and on the output side, which switch is connected to a respective clock signal input for its control. 25 bits may be necessary, for example, for addressing a 256-megabit SD RAM chip. Accordingly, 25 circuit configurations of the type described may be provided for the addressing and storage of the address of a defective memory cell in the SDRAM chip. In this case, the shift registers may be serially connected to one another to form a shift register chain via switches respectively provided on the input side and on the output side. This enables a clock-controlled read-in of data into the respective memory cells of the volatile memories, a read-out of data from the volatile memories with the register chain, and also an activation of drive circuits or blowing transistors for blowing programmable links likewise by the shift register chain.
In a further preferred embodiment of the invention, the switches in the shift register are CMOS transfer gates. The latter enable a particularly fast, serial data transfer for writing and reading.
In a further preferred embodiment of the present invention, the shift register has a further memory cell, which, on the output side, is connected to the switch connected downstream of the register cell. The further memory cell may be coupled to the output of the memory cell of the volatile memory for reading from the volatile memory.
In a further preferred embodiment of the present invention, the circuit configuration is constructed using CMOS circuit technology. This makes it possible to realize the circuit configuration with a particularly low current requirement and area requirement.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for driving a programmable link, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.